1. Technical Field
The disclosure relates generally to controlling across-chip-length-variation (ACLV) during formation of a semiconductor structure in complementary metal oxide semiconductor (CMOS) circuits fabrication, and more particularly, to methods of forming coplanar active areas and isolation areas and structures thereof.
2. Background Art
In the current state of the art, continued complimentary metal oxide semiconductor (CMOS) scaling includes scaling of gate structures. With scaling of gate structures, across-chip-length-variation (ACLV) of length of gate structures becomes difficult to control. This difficulty arises from shallow-trench-isolation (STI) surfaces being non-coplanar with surfaces of active silicon regions in gate structures.
A small or good ACLV requires good control over the distance between a lithographic lens and the photo resistance surface to which the lithographic lens is focused. If the surface to which the lithographic lens is focused changes and is not level, control of the distance becomes difficult both within a wafer and/or a chip. Therefore, a flat surface as a starting point for critical lithography is preferred.